Jitter Measurements for CLK Generators or Synthesizers - Application Note - Maxim

Clock (CLK) generators and synthesizers form the pulse of a complex digital system and errors in a clock's signal quality can have wide-ranging effect. One of the most important performance measurements is clock jitter. Jitter is defined as "the short-term variation of a signal with respect to its ideal position in time." In a clock generator chip, there are many factors which contribute to output clock jitter, such as the device noise, supply variation, jitter in the reference clock, loading condition, and interference coupled from nearby circuitry. Jitter can be measured in different ways, including period jitter JPER, cycle-to-cycle jitter JCC, and accumulated jitter JACC. In general, jitter consists of the deterministic jitter and random jitter. Since the deterministic jitter in most digital systems is introduced frommany different bit patterns from the digital data, clock signal jitter can usually be considered to be just random jitter. In this application note, we will go over the definitions and introduce test setups for making measurements. Jitter Definitions Period Jitter: JPER Jitter JPER is the most popular jitter measure. It is the time difference between a measured cycle period and the ideal cycle period. Due to its random nature, this jitter can be measured as Peak-to-Peak or by Root Mean Square (RMS). Let's define the clock rising edge crossing point at the threshold VTH as TPER(n), where n is the time domain index, as shown in Figure 1. Mathematically, we can describe JPER as where T0 is the ideal clock cycle. Figure 1 shows the relation between JPER and TPER in a clock waveform.